The present invention relates to a process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), and more particularly to a simplified process for forming the TFT matrix with reduced masking steps.
For conventional manufacturing processes of a TFTLCD, six to nine masking steps are required for forming the TFT matrix. One of the processes, which is a 6-mask one, is illustrated as follows.
The conventional process includes steps of:
i) applying a first conductive layer onto a glass substrate 10, and using a first photo-masking and lithography procedure to pattern and etch the first conductive layer to form an active region 12 consisting of a scan line and a gate electrode of a TFT unit, as shown in FIG. 1A;
ii) sequentially forming an insulation layer 14, an amorphous silicon (a-Si) layer 16, an n+ amorphous silicon layer 18 and a photoresist 19 on the resulting structure of FIG. 1A, as shown in FIG. 1B, and exposing the resulting structure from the back side of the substrate, as indicated by arrows, wherein a portion of the photoresist 19 above the region 12 is shielded by the region 12 from exposure so as to exhibit a self-aligned effect;
iii) etching off the exposed photoresist 19, portions of the layers 16 and 18 thereunder, and the remaining photoresist so that each of the remaining layers 16 and 18 has a shape substantially identical to the region 12, and using a second photo-masking and lithography procedure to pattern and etch the layers 16 and 18 again to isolate the TFT unit 11, as shown in FIG. 1C;
iv) using a third photo-masking and lithography procedure to further pattern and etch the layers 16 and 18 to form a tape automated bonding (TAB) contact window for the scan line (not shown);
v) applying an indium tin oxide (ITO) layer on the resulting structure of FIG. 1C, and using a fourth photo-masking and lithography procedure to pattern and etch the ITO layer to form a pixel electrode 20 by a single side of the TFT unit 11, as shown in FIG. 1D;
vi) applying a second conductive layer on the resulting structure of FIG. 1D, using a fifth photo-masking and lithography procedure to pattern and etch the second conductive layer to integrally form a data line 23, a first connection line 22a between the TFT unit 11 and the data line 23, and a second connection line 22b between the TFT unit 11 and the pixel electrode 20, and using the remaining second conductive layer as a shield to etch off a portion of the doped a-Si layer 18 between the connection lines 22a and 22b to separate the source/drain electrodes 111 of the TFT unit 11, as shown in FIG. 1E; and
vii) applying a passivation layer 24 on the resulting structure of FIG. 1E, and using a sixth photo-masking and lithography procedure to pattern and etch the passivation layer 24 to expose the TAB contact window for the scan line, create a TAB contact window for the data line (not shown), and create an opening window A for the pixel electrode 20.
As known, the count of photo-masking and lithography steps directly affects not only the production cost but also the manufacturing time. Moreover, for each photo-masking and lithography step, the risks of mis-alignment and contamination may be involved so as to affect the production yield. The complicated 6-mask process mentioned as above thus results in relatively high cost and relatively low yield.
For current techniques, the above steps ix) and vii) can be combined to achieve a 5-mask process owing to the improvement on material. That is, all the TAB contact windows can be formed by a single masking and patterning step.
In order to further reduce the count of photo-masking and lithography steps, many efforts have been made to develop new processes. For example, U.S. Pat. Nos. 5,346,833 and 5,478,766 issued to Wu and Park et al., respectively, disclose 3 and/or 4-mask processes for making a TFTLCD, which are incorporated herein for reference. It is to be noted that the 3-mask process for each of Wu and Park et al. does not include the step of forming and patterning of a passivation layer. If a passivation layer is required to assure of satisfactory reliability, the count of photo-masking and lithography steps should be four.
Although Wu and Park et al. disclose the processes of reduced masks, the use of the ITO layer, which is integrally formed with the ITO pixel electrode, as the connection line between the TFT unit and the data line limits the area of the TFTLCD due to the high resistivity of ITO.
Therefore, an object of the present invention is to provide a reduced mask process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), in which the connection line between the TFT unit and the data line has a relatively low resistivity compared to the ITO connection line so as to be suitable for a large-area TFTLCD.
Another object of the present invention is to provide a four-mask process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD).
According to a first aspect of the present invention, a process for forming a TFT matrix for an LCD includes steps of: providing a substrate made of an insulating material; forming a first conductive layer on a first side of the substrate, and using a first masking and patterning procedure to form a scan line and a gate electrode of a TFT unit; successively forming an insulation layer, a semiconductor layer, a doped semiconductor layer, and a photoresist layer on the substrate with the scan line and the gate electrode; providing an exposing source from a second side of the substrate opposite to the first side by using the scan line and the gate electrode as shields to form an exposed area and an unexposed area; removing the photoresist, the doped semiconductor layer, and the semiconductor layer of the exposed area so that the remained portion of the semiconductor and the doped semiconductor layers in the unexposed area has a specific shape substantially identical to the shape of the scan line together with the gate electrode; forming a second conductive layer on the substrate with the semiconductor and the doped semiconductor layers of the specific shape, and using a second masking and patterning procedure to integrally form a data line, a first connection line between the TFT unit and the data line, and a second connection line connecting to the TFT unit; removing a portion of the doped semiconductor layer with the data line, and the first and the second connection lines as shields; and forming a transparent conductive layer on the substrate with the data line, and the first and the second connection lines, and using a third masking and patterning procedure to form a pixel electrode which is connected to the TFT unit through the second connection line.
When the exposing source is a light radiation, the insulating material is a light-transmitting material such as glass.
Preferably, the first conductive layer is formed of chromium, tungsten molybdenum, tantalum, aluminum or copper.
Preferably, the insulation layer is formed of silicon nitride, silicon oxide, silicon oxynitride, tantalum oxide or aluminum oxide.
Preferably, the semiconductor layer is formed of amorphous silicon, micro-crystalline silicon or polysilicon.
Preferably, the doped semiconductor layer is formed of n+ amorphous silicon, n+ micro-crystalline silicon or n+ polysilicon.
Preferably, the second conductive layer is a Cr/Al or a Mo/Al/Mo composite layer.
Preferably, the transparent conductive layer is formed of indium tin oxide, indium zinc oxide or indium lead oxide, and applied by sputtering. On the other hand, the patterned transparent conductive layer is located by a single side of the TFT unit.
Preferably, the process further includes a step of forming a passivation layer on the substrate to protect the data line, and the first and the second connection lines, and using a fourth masking and patterning procedure to define an isolation window area, and create a contact hole. The formation of the passivation layer is performed after the step of removing the portion of the doped semiconductor layer with the data line, and the first and the second connection lines as shields. Then, a step of removing a portion of the semiconductor layer in the isolation window area with the patterned passivation layer as a shield is performed to form an isolation window for cutting off the connection of the TFT unit with the data line through the semiconductor layer. Moreover, the transparent conductive layer extends into the contact hole to connect to the second connection line.
Preferably, the passivation layer is formed of silicon nitride or silicon oxynitride.
According to a second aspect of the present invention, a process for forming a TFT matrix for an LCD includes steps of: providing a light-emitting substrate; forming a first conductive layer on the substrate at a first side hereof; using a first photo-mask to pattern the first conductive layer as a scan line and a gate electrode of a TFT unit; sequentially forming an insulation layer, a semiconductor layer, and a doped semiconductor layer over the substrate with the scan line and the gate electrode; using the scan line and the gate electrode as shields, and a radiation light from a second side of the substrate opposite to the first side as an exposing source to pattern the semiconductor and the doped semiconductor layers to define source/drain electrodes of the TFT unit; forming a second conductive layer over the substrate with the patterned semiconductor and doped semiconductor layers; using a second photo-mask to pattern the second conductive layer as a data line, a first connection line between the TFT unit and the data line, and a second connection line connecting to the TFT unit; using the data line, and the first and the second connection lines as shields to remove a portion of the doped semiconductor layer to define an isolation window area; forming a passivation layer over the substrate with the patterned second conductive layer; using a third photo-mask to pattern the passivation layer to simultaneously uncover the isolation window area, create a contact hole for exposing a portion of the second connection line, and create a tape automated bonding (TAB) window for exposing a portion of the scan line and the data line; and using the patterned passivation layer as a shield to remove a portion of the semiconductor layer in the isolation window area to form an isolation window; forming a transparent conductive layer on the substrate with the patterned passivation layer; and using a fourth photo-mask to pattern the transparent conductive layer as a pixel electrode which extends into the contact hole to connect with the TFT unit through the second connection line.
Preferably, the insulating material is glass; the first conductive layer is selected from a chromium, a tungsten molybdenum, a tantalum, an aluminum and a copper layers; the second conductive layer is selected from a Cr/Al and a Mo/Al/Mo composite layers; the insulation layer is formed of a material selected from silicon nitride, silicon oxide, silicon oxynitride, tantalum oxide and aluminum oxide; the semiconductor layer is formed of a material selected from amorphous silicon, micro-crystalline silicon and polysilicon; the doped semiconductor layer is formed of a material selected from highly doped amorphous silicon, micro-crystalline silicon and polysilicon; the passivation layer is formed of a material selected from silicon nitride and silicon oxynitride; and the transparent conductive layer is formed of a material selected from indium tin oxide, indium zinc oxide and indium lead oxide.
According to a third aspect of the present invention, a process for forming a TFT matrix for an LCD includes steps of: providing a substrate made of an insulating material; forming a first conductive layer of a first pattern on a first side of the substrate as a scan line and a gate electrode of a TFT unit; forming an insulation layer over the scan line and the gate electrode; forming a semiconductor and a doped semiconductor layers of a second pattern substantially identical to the first pattern on the insulation layer for defining a source and a drain electrodes of the TFT unit; forming a second conductive layer of a third pattern over the semiconductor and the doped semiconductor layers of the second pattern as a data line, a first connection line between the TFT unit and the data line, and a second connection line connecting to the TFT unit; removing a portion of the semiconductor and the doped semiconductor layers to create an isolation window for cutting off the connection of the TFT unit with the data line through the semiconductor and the doped semiconductor layers; removing another portion of the doped semiconductor layer to isolate the source electrode from the drain electrode of the TFT unit; forming a passivation layer of a fourth pattern over the second conductive layer which includes a contact hole to expose a portion of the second connection line; and forming a transparent conductive layer of a fifth pattern over the passivation layer as a pixel electrode, which further extends into the contact hole to connect with the second connection line.